Commit f64d434d authored by Oscar Bejarano's avatar Oscar Bejarano Committed by Oscar

Add AGC init to sounder

Minor bug fix
parent b2b70d11
......@@ -31,4 +31,24 @@
#define FPGA_IRIS30_INCR_TIME (1 << 2)
#define FPGA_IRIS30_DECR_TIME (1 << 3)
// AGC and Packet Detect
#define FPGA_IRIS030_WR_AGC_ENABLE_FLAG 232
#define FPGA_IRIS030_WR_AGC_RESET_FLAG 236
#define FPGA_IRIS030_WR_IQ_THRESH 240
#define FPGA_IRIS030_WR_NUM_SAMPS_SAT 244
#define FPGA_IRIS030_WR_MAX_NUM_SAMPS_AGC 248
#define FPGA_IRIS030_WR_RSSI_TARGET 252
#define FPGA_IRIS030_WR_WAIT_COUNT_THRESH 256
#define FPGA_IRIS030_WR_AGC_SMALL_JUMP 260
#define FPGA_IRIS030_WR_AGC_BIG_JUMP 264
// RSSI register Set
#define FPGA_IRIS030_RD_MEASURED_RSSI 284
// Packet Detect Register Set
#define FPGA_IRIS030_WR_PKT_DET_THRESH 288
#define FPGA_IRIS030_WR_PKT_DET_NUM_SAMPS 292
#define FPGA_IRIS030_WR_PKT_DET_ENABLE 296
#define FPGA_IRIS030_WR_PKT_DET_NEW_FRAME 300
#endif
......@@ -31,6 +31,7 @@ public:
void radioRx(void* const* buffs);
int radioTx(size_t, const void* const* buffs, int flags, long long& frameTime);
int radioRx(size_t, void* const* buffs, long long& frameTime);
void initAGC(SoapySDR::Device * iclSdrs);
void sync_delays(int cellIdx);
~RadioConfig();
......
......@@ -168,6 +168,10 @@ RadioConfig::RadioConfig(Config* cfg)
reset_DATA_clk_domain(dev);
radios[i].rxs = dev->setupStream(SOAPY_SDR_RX, SOAPY_SDR_CF32, channels);
radios[i].txs = dev->setupStream(SOAPY_SDR_TX, SOAPY_SDR_CF32, channels);
if (_cfg->clAgcEn){
RadioConfig::initAGC(dev);
}
}
}
std::cout << "radio init done!" << std::endl;
......@@ -762,6 +766,31 @@ void RadioConfig::collectCSI(bool& adjust)
}
}
void RadioConfig::initAGC(SoapySDR::Device * iclSdr)
{
/*
* Initialize AGC parameters
*/
// AGC Core
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_AGC_ENABLE_FLAG, 0); // Enable AGC Flag (set to 0 initially)
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_AGC_RESET_FLAG, 1); // Reset AGC Flag
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_IQ_THRESH, 1000); // Saturation Threshold: 10300 about -6dBm
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_NUM_SAMPS_SAT, 3); // Number of samples needed to claim sat.
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_MAX_NUM_SAMPS_AGC, 100); // Threshold at which AGC stops
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_WAIT_COUNT_THRESH, 20); // Gain settle takes about 20 samps(value=20)
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_AGC_BIG_JUMP, 30); // Drop gain at initial saturation detection
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_AGC_SMALL_JUMP, 2); // Drop gain at subsequent sat. detections
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_RSSI_TARGET, 20); // RSSI Target for AGC: ideally around 14 (3.6GHz) or 27 (2.5GHz)
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_AGC_RESET_FLAG, 0); // Clear AGC reset flag
// Packet Detect Core
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_PKT_DET_THRESH, 0); // RSSI value at which Pkt is detected
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_PKT_DET_NUM_SAMPS, 5); // Number of samples needed to detect frame
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_PKT_DET_ENABLE, 0); // Enable packet detection flag
iclSdr->writeRegister("IRIS30", FPGA_IRIS030_WR_PKT_DET_NEW_FRAME, 0); // Finished last frame? (set to 0 initially)
}
void RadioConfig::drain_buffers(SoapySDR::Device* ibsSdrs, SoapySDR::Stream* istream, std::vector<void*> buffs, int symSamp)
{
/*
......
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